1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, More particularly the invention is directed to a method for planarizing the Field OXide (FOX) on a silicon substrate formed by the LOCal Oxidation of Silicon (LOCOS).
2. Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on the semiconductor substrate is in part due to advances in high resolution photolithographic techniques and to advances in plasma etching of the various conducting and insulating layers on the substrate. However, the accumulated effect of depositing and etching of patterns in these layers, one patterned layer on top of the other, has resulted in irregular or substantially non-planar surfaces with micrometer and submicrometer feature sizes on an otherwise microscopically planar substrate.
These irregular surface features cause a number of process and reliability problems. For example, during plasma etching to pattern conducting layers, the directional or anisotropic etching can leave residue, often referred to as rails or stringers at the edges of the underlying surfaces irregularities. This results from the fact that conformal conducting layers formed over steps are thicker in the vertical direction on the sidewall of the step than they are on the horizontal surface. The directionality of the plasma etching which etches predominantly in the vertical direction leaves residue from the conducting layer on the sidewalls of the step. This then results in electrical shorts between adjacent patterned conducting layers that are used to connect or wire up the various devices.
One processing area where this residue can be a major problem is the patterning by anisotropic etching of the polysilicon gate electrode for FETs and the word and bit lines that are used on integrated circuit, such as on DRAMS, SRAMs and microprocessor chips.
This problem can be better understood by referring to FIGS. 1 and 2. In FIG. 1 is shown a schematic cross-section of a substrate 10 having a typical device area 5 whereon the gate electrode of the FET is formed and with a Field OXide (FOX) structure 12 formed in and on the silicon substrate 10 and surrounding the device area. Typically the conventional field oxide isolation 12 is formed using a LOCal Oxidation of Silicon (LOCOS) process in which the device area 5 is masked with a thin protective pad oxide 14 and a thicker silicon nitride layer 16 that is a barrier to oxidation. The silicon substrate is then oxidized to form the field oxide 12 having a thickness of about 4500 to 5500 angstroms.
By the nature of the oxidation, which results in a volume expansion, approximately one half of the oxide thickness extends above the original substrate surface and about one half below the surface. In addition, portions of this thermally grown oxide near the silicon nitride edge are highly stressed, as indicated by an A in FIG. 1. These highly stained areas tend to etch at a faster rate when wet etched, for example, when the pad oxide layer 14 is removed in a buffered hydrofluoric acid.
As shown in FIG. 2, when the silicon nitride layer 16 and the pad oxide layer 14 are removed from over the device area 5 and a polysilicon gate electrode 18 is patterned over a thin gate oxide 15 by photoresist masking and anisotropic etching, there remains on the edge of the field oxide residual polysilicon 18' which is difficult to remove without excessive over etching.
The reliability of conducting lines formed over large steps in the underlying substrate is also of major concern. For example, thinning of the line or voids formed therein can be a source of electrical failure when the circuit is powered up.
One general approach in the semiconductor industry to circumvent these topographic problems, is to provide a planar surface on which the conducting layer is patterned. A method commonly used to form a planar field oxide, is to first recess the silicon substrate in the field oxide area by etching a trench and then growing a thermal oxide therein. Alternatively, the recess can be filled using a chemical vapor deposited (CVD) silicon oxide and then planarized, for example, by chemical/mechanical polishing the CVD oxide to remove the raised portion of the CVD oxide. Another approach is to fill the recess with CVD oxide and then planarize the CVD oxide by applying a leveling material such as spin-on-glass (SOG) and etching back the SOG and the CVD to the substrate surface using a non-selective plasma etching. This later approach using a CVD oxide filled recess process is described by T. Otsu in U.S. Pat. No. 5,236,861. Another method for forming a planar thermal oxide in a recessed field oxide area is described by G. Burton in U.S. Pat. No. 4,539,744.
Although recessing the field oxide area and then filling with a deposited or thermally grown oxide, is a viable process, there are a number of concerns. For example, forming recesses in the single crystal silicon substrate having sharp corners and then forming a thick thermal oxide can lead to crystalline defects that can degrade device performance. Also the process complexity is increased with increasing manufacturing costs. Therefore, there is a strong need to provide a simple and effective method for forming a planar field oxide without the necessity of forming recesses in the silicon substrate.